Integrated classifier simulator and neurochip VHDL implementation

Autor:	O. B. Efremides, David J. Evans, Michael P. Bekakos
Rok vydání:	2003
Předmět:	Computer architecture simulator business.industry Computer science Applied Mathematics Computer Science Applications Neurochip Computational Theory and Mathematics Embedded system Component-based software engineering VHDL business computer Classifier (UML) Java Programming Language Simulation computer.programming_language
Zdroj:	International Journal of Computer Mathematics. 80:1343-1350
ISSN:	1029-0265 0020-7160
DOI:	10.1080/0020716031000148223
Popis:	In this work, the development of a simulator for a system capable of recognizing and classifying patterns into certain classes (families) is investigated. The classification system integrating hardware and software components is presented. The entire system simulator is developed using Java programming language, while its hardware parts are implemented and simulated using VHDL.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::94e0f04978f442e3c6b587bdcfbf9ca4 https://doi.org/10.1080/0020716031000148223 Zobrazit plný text záznamu Plný text ve formátu PDF Plný text ve formátu HTML
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