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We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin film transistors (TFTs) with a self-aligned-gate process to fabricate high speed circuits. Sputter deposited ZnO films have been widely studied, but there have been few reports of dense thin films and high performance devices and circuits. Atomic layer deposition (ALD) of ZnO has been shown to be a very uniform and conformal process, but ALD ZnO films typically have high background carrier concentration and require doping compensation for enhancement-mode TFTs. PEALD provides the uniform conformal coating of ALD and enhancement-mode devices from uncompensated films. Our PEALD ZnO TFTs have linear field-effect mobility >20 cm2/V⋅s and saturation field-effect mobility >30 cm2/V⋅s and PEALD ring oscillators with beta ratio ~5, channel length ~2.8 µm, and ~1.5 µm gate-source/drain overlap operate at ~25 ns/stage. Recently, scaled indium-gallium-zinc oxide ring oscillator circuits on silicon substrates (0.5 µm channel length, and 0.5 µm overlap) were reported to operate at ~7 ns/stage with a saturated-load inverter design, and < 1 ns/stage with a novel bootstrapped inverter design [1]. The speed of our previous PEALD circuits [2] was largely limited by the parasitic capacitance between the gate and drain, and a self-aligned-gate process would provide higher speed devices and circuits. Here we have report a simple self-aligned-gate process for ZnO TFTs and high speed circuits. |
