Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack
| Autor: | Kundan Nepal, Jennifer Dworak, Fanchen Zhang, Theodore W. Manikas, Hui Jiang, Yi Sun, R. Iris Bahar |
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| Rok vydání: | 2019 |
| Předmět: |
business.product_category
Exploit Computer science business.industry 020208 electrical & electronic engineering SerDes Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Integrated circuit Field (computer science) 020202 computer hardware & architecture law.invention Stack (abstract data type) law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Die (manufacturing) Electrical and Electronic Engineering Field-programmable gate array business Repurposing Computer hardware |
| Zdroj: | Journal of Electronic Testing. 35:887-900 |
| ISSN: | 1573-0727 0923-8174 |
| Popis: | We propose an architecture for a Field Programmable Gate Array (FPGA) based tester for a 3D stacked integrated circuit (IC). Due to the very short distances between dies in a stack that can make SerDes connections very efficient and the high density of through silicon vias (TSVs) that may be available, it is possible to connect the FPGA to the die under test through a very high bandwidth connection that can feed multiple short scan chains. We propose and evaluate two designs that exploit the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns, reducing the FPGA resources required and the switching activity in the circuit under test when compared to a more traditional on-chip decompressor implemented to feed short scan chains. For the largest circuit we studied, the switching activity was reduced about 80% and the test time by 90%. |
| Databáze: | OpenAIRE |
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