A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

Autor:	Byung-Hun Min, Hyun-Kyu Yu, Seong-Do Kim, Mi-Jeong Park, Mun-Yang Park, Ja-Yol Lee
Rok vydání:	2012
Předmět:	Phase-locked loop Engineering business.industry Settling time Low-power electronics Dynamic demand Phase noise Electronic engineering dBc Electrical and Electronic Engineering business Noise (electronics) Power (physics)
Zdroj:	IEEE Transactions on Circuits and Systems I: Regular Papers. 59:1706-1719
ISSN:	1558-0806 1549-8328
DOI:	10.1109/tcsi.2012.2206500
Popis:	This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves -97 dBc in-band phase noise, - 38 dBc/Hz integrated noise, and 740 ns settling time.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::94aecfaea8732b3b110ade1ee15cb58f https://doi.org/10.1109/tcsi.2012.2206500 Zobrazit plný text záznamu