| Autor: |
Won-Cheol Lee, Hong-June Park, Byungsub Kim, Kihwan Seong, Jae-Yoon Sim |
| Rok vydání: |
2016 |
| Předmět: |
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| Zdroj: |
JSTS:Journal of Semiconductor Technology and Science. 16:352-358 |
| ISSN: |
1598-1657 |
| DOI: |
10.5573/jsts.2016.16.3.352 |
| Popis: |
A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5- phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies 0.038 mm², consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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