Spare block cache (SprBlk): Fault resilience and reliability at low voltages
| Autor: | Nafiul Alam Siddique, Abdel-Hameed A. Badawy |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Adder Hardware_MEMORYSTRUCTURES Computer science business.industry CPU cache Cache-only memory architecture Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Fault (power engineering) 01 natural sciences 020202 computer hardware & architecture 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Cache Fault model business Low voltage Computer hardware Block (data storage) |
| Zdroj: | SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI |
| DOI: | 10.1109/uic-atc.2017.8397619 |
| Popis: | This paper proposes a novel cache architecture that uses spare cache blocks to work as back up blocks in a set associative cache, which can operate reliably at voltages well below the manufacturing induced operating voltage (V ccmin ). We detect errors in all cache lines at low voltage (i.e. persistent error), tag them as either faulty or fault-free. At runtime, we bypass the faulty words. To bypass faulty words, we use adder and shifter circuitry. Furthermore, we develop a fault model to find the cache set failure probability at low voltage. At 485 mV, SprBlk cache operates with a 16.7% lower bit failure probability compared to a conventional cache operating at 782 mV. Additionally, SprBlk reduce power consumption by 1% when implemented in the L1 data cache only, by 75% when implemented in the L2 cache only, and by 76% when implemented in both caches. |
| Databáze: | OpenAIRE |
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