IBM's S/390 G5 microprocessor design
| Autor: | T.J. McPherson, J. D. MacDougall, John Stephen Liptay, R. Averill, J.A. Navarro, C.A. Krygowski, C. Kevin Shum, B.C. Giamei, Eric M. Schwarz, M.A. Check, T.J. Slegel, Barry Watson Krumm, W.H. Li, Charles F. Webb |
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| Rok vydání: | 1999 |
| Předmět: |
IBM SAN Volume Controller
IBM 8514 Reduced instruction set computing Cellular architecture Computer science computer.software_genre law.invention IBM POWER microprocessors IBM Floating Point Architecture Microprocessor Computer architecture Hardware and Architecture law Operating system Index register Central processing unit Electrical and Electronic Engineering computer Software Channel I/O Word (computer architecture) Complex instruction set computing |
| Zdroj: | IEEE Micro. 19:12-23 |
| ISSN: | 0272-1732 |
| Popis: | The IBM S/390 G5 microprocessor in IBM's newest CMOS mainframe system provides more than twice the performance of the previous generation, the G4. The G5 system offers improved reliability and availability, along with new architectural features such as support for IEEE floating-point arithmetic and a redesigned L2 cache and processor interconnect. The G5 system implements the ESA/390 instruction-set architecture, which is based on and compatible with the original S/360 architecture. Therefore, it has no RISC (reduced-instruction-set computing) concepts and is one of the most complex of all CISC (complex-instruction-set computing) architectures. Designers had to meet a unique set of challenges to achieve the G5's level of performance-for example, achieving a very high frequency given the complexity of the architecture. |
| Databáze: | OpenAIRE |
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