A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery

Autor:	Kuk-Tae Hong, Seung-Hyun Yi, Byong Chan Lim, Sung-Hyun Yang, Tae-Young Oh
Rok vydání:	2006
Předmět:	Phase-locked loop Time-to-digital converter CMOS Computer science Phase noise Hardware_INTEGRATEDCIRCUITS Electronic engineering Hardware_PERFORMANCEANDRELIABILITY Digitally controlled oscillator Phase frequency detector Clock recovery Jitter
Zdroj:	CICC
DOI:	10.1109/cicc.2006.320966
Popis:	This paper presents a digital PLL for low long-term jitter clock recovery. A jitter reduction scheme for digitally controlled oscillator is proposed and 39% jitter reduction is observed. A 5-phase digital phase frequency detector (PFD) has 265 ps resolution and controls output clock phase by 132 ps step. The long-term jitter is measured as 460 ps pk-pk. This digital PLL is implemented in 0.18 ?m CMOS process using 0.417 mm2 and consumes 61.0 mW power.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::93e33c42a9de62f841d6a1fa12a9dbca https://doi.org/10.1109/cicc.2006.320966 Zobrazit plný text záznamu