A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS
| Autor: | Taeho Jeon, Yujong Noh, Heejoung Park, Won-Sun Park, Chang-Hyuk Lee, Yo-Hwan Koh, In-Suk Yun, Chul-Woo Yang, Jinhaeng Lee, Moonsoo Sung, Sunghoon Ahn, Joong-Seob Yang, Yongdeok Cho, Hyunjong Jin, Sanghwan Kim, Jooyun Ha, Jeawon Choi, Chae-Kyu Jang, Sanghwa Chung, Byoung-In Joo, Jee-Yul Kim, Jeakwan Kwon, Sok-Kyu Lee, Jeong Byoung Kwan, Dae-Il Choi |
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| Rok vydání: | 2011 |
| Předmět: | |
| Zdroj: | IEEE Journal of Solid-State Circuits. 46:97-106 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2010.2084450 |
| Popis: | Novel program and read schemes are presented to break barriers in scaling of NAND flash memory such as threshold voltage endurance from floating gate interference, and charge loss tolerance. To enhance threshold voltage endurance and charge loss tolerance, we introduced three schemes; MSB Re-PGM scheme, Moving Read scheme and Adaptive Code Selection scheme. Using the MSB Re-PGM scheme, threshold voltage distribution width is improved about 200 mV. The PGM throughput is enhanced from 1500 μs to 1250 μs. With the Moving Read scheme about half order of UBER is improved with 10 bit ECC. Also, Adaptive Code Selection scheme are used to decrease a current consumption. There is 5.5% current reduction. With these techniques, 32-Gb MLC NAND flash memory has been fabricated using a 32 nm CMOS process technology. Its program throughput reaches 13.0 MB/s at a multi-plane program operation with cache operation keeping a desirable threshold voltage distribution. |
| Databáze: | OpenAIRE |
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