Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology
| Autor: | D. DeSalvo, M. Baze, M. Dooley, B. Hughlock, B. Rasmussen, K. Gerst, A. Le, M. Yoo, D. Nardi, I. Ojalvo, K. Kohnen, E. Zayas, D. Sunderland, R.D. Jobe, B. Jeppson, J. Truong, D.L. Hansen, A. Kleinosowski, K. Amador, E.J. Miller, D. Wong |
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| Rok vydání: | 2009 |
| Předmět: |
Nuclear and High Energy Physics
Engineering Pass transistor logic business.industry Logic family Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention Nuclear Energy and Engineering CMOS law Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business Flip-flop Hardware_LOGICDESIGN Asynchronous circuit Logic optimization |
| Zdroj: | IEEE Transactions on Nuclear Science. 56:3542-3550 |
| ISSN: | 1558-1578 0018-9499 |
| Popis: | Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to single event effects (SEE). The variables characterized included: well structure on the wafer, density of well contacts, logic data pattern, angle of indicence, flip-flop redundancy, variation in sensitive node spacing, and the effect of transients as a function of combinatorial logic type. Analysis of the cross section contribution from the clock, flip-flop and SET target circuitry showed that any hardening technique used in a production integrated circuit may be limited in its effectiveness due to other circuits and logic in the integrated circuit. |
| Databáze: | OpenAIRE |
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