| Popis: |
Implementing artificial neural network (ANN) on hardware, e.g. as hard IP in SoC or soft IP in FPGA, for acceleration is one of the common methods to obtain high performance. Being the heart of ANN, the performance of artificial neuron directly determines the performance of the entire system. Artificial neuron’s algorithm comprises of two portions, sum-of-product for input connection and activation function. Due to looped calculation required for sum-of-product and non-linearity calculation of activation function, implementing an artificial natively will yield a very low efficiency performance. This paper presents an under-going work that illustrate the use of several technique, such as pipelining and hierarchical distributed adder, to achieve high performance artificial neuron. Our measured result shows that it takes about 528 clock cycles for the artificial neuron to complete processing for 8 input connections. The performance is estimated to increase by 82 % with proposed technique. |
