Concurrent error detection in self-timed VLSI

Autor:	Hyeongil Kim, David Rennels
Rok vydání:	2002
Předmět:	Very-large-scale integration Signal generator Computer engineering Comparator Computer science Redundancy (engineering) Logic family Electronic engineering Cascode Error detection and correction Electronic circuit
Zdroj:	FTCS
DOI:	10.1109/ftcs.1994.315653
Popis:	This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are compared with a checker that is composed of a tree of dual-rail (morphic) comparators to detect errors and signal completion. An efficient implementation is shown that compares favorably in speed and area with conventional completion signal generators. A simple pipeline is examined with error checkers at each computation stage and hand-shaking control circuits that are modified to improve error detection. Its error-detecting properties are discussed, and preliminary error simulation results are presented. Based on these studies we have concluded that self-timed logic offers considerable fault-tolerance potential due to its built-in redundancy that can be effectively exploited for error checking. >
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::92bff3b63387515a0dfe79a6124fb8bf https://doi.org/10.1109/ftcs.1994.315653 Zobrazit plný text záznamu