3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability
| Autor: | Amey Mahadev Walke, Anne Vandooren, F. M. Bufler, Nancy Heylen, J. Franco, Bich-Yen Nguyen, Gweltaz Gaudin, Lieve Teugels, Veeresh Deshpande, Boon Teik Chan, Dan Mocuta, Walter Schwarzenbach, T. Zheng, W. Li, Z. Wu, Erik Rosseel, Niamh Waldron, Nadine Collaert, E. Vecchio, Nouredine Rassoul, Romain Ritzenthaler, V. De Heyn, Bertrand Parvais, W. Vanherle, Liesbeth Witters, Iuliana Radu, G. Verbinnen, Lan Peng, Fumihiro Inoue, Andriy Hikavyy, Geert Hellings, Katia Devriendt, G. Jamieson, G. Besnard |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Materials science Wafer bonding business.industry 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Electronic Optical and Magnetic Materials PMOS logic CMOS Logic gate 0103 physical sciences Optoelectronics Wafer Electrical and Electronic Engineering 0210 nano-technology Metal gate business NMOS logic High-κ dielectric |
| Zdroj: | IEEE Transactions on Electron Devices. 65:5165-5171 |
| ISSN: | 1557-9646 0018-9383 |
| Popis: | 3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at ${V}_{\textsf {G}}= {V}_{\textsf {th}}+ 0.6$ V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer. |
| Databáze: | OpenAIRE |
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