A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory
| Autor: | Yun-Chung Yang, Hsu-Kang Dow, Ing-Jer Huang, Chun-Hung Lai, Hung-Lun Chen |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Random access memory Hardware_MEMORYSTRUCTURES business.industry Computer science CPU cache 02 engineering and technology 01 natural sciences 020202 computer hardware & architecture law.invention Microprocessor Memory management Tag RAM Hardware and Architecture law Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Overhead (computing) System on a chip Cache Electrical and Electronic Engineering business Software Register-transfer level |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26:663-670 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2017.2785222 |
| Popis: | The cache memory has been a predominant component in modern chips, easily taking up more than 50% of the silicon area. It is then desirable to make the cache memory flexible for different needs. Therefore, many modern processor chips allow users to configure a part of the cache memory as the scratch-pad memory (SPM), a high-speed internal memory for rapid data access. However, such approach uses only the data RAM of the cache memory while leaving the tag RAM unused and thus wasting its capacity. This paper presents a cache organization, called Tag-SPM architecture, which allows the tag RAM to be used as the SPM and thus increases its capacity. It is accomplished with small Tag/Data-SPM controllers and four additional multiplexers in the cache organization. The proposed Tag-SPM architecture has been implemented with an academic ARM-based microprocessor with 4-/4-kB four-way set-associative instruction/data caches at the register transfer level level. Experiments show that the proposed architecture boosts the SPM capacity by 12.5% and requires only 0.08% area (434 gates) overhead without impairing the cache’s circuit speed in TSMC’s 90-nm standard cell implementation. Furthermore, the power overhead is negligible. When the Tag-SPM architecture is applied to typical cache systems, such as in ARM’s Cortex-A5 and Cortex-A53 processors, additional 12.5% SPM space per way can also be gained in both cases. The analyses show that our Tag-SPM architecture is a highly cost-effective way to boost the SPM space. |
| Databáze: | OpenAIRE |
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