| Autor: |
P. Schuddinck, Stefan Kubicek, Nadine Collaert, M. Garcia-Bardon, Aaron Thean, Raja Athimulam, Steven Demuynck, Ingrid Debusschere, Mustafa Badaroglu, L. Altimime, Naoto Horiguchi, Diederik Verkest, Michele Stucchi, Thomas Chiarella, Abdelkarim Mercha, Arindam Mallik, Andriy Hikavyy |
| Rok vydání: |
2012 |
| Předmět: |
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| Zdroj: |
2012 International Electron Devices Meeting. |
| DOI: |
10.1109/iedm.2012.6479101 |
| Popis: |
It is shown that the performance impact of middle-of-line (MOL) patterning process variations can be reduced by 30% by relaxing the standard cell gate pitch by 10% in both 20nm bulk planar (BPL) and 14nm bulk finFET (BFF). Tungsten can safely replace copper in local interconnect IM2, which allows the MOL critical dimensions (CD) to be reduced by 40% in 20nm BPL, resulting in 5% performance improvement. In 14nm BFF, 10% performance degradation can be traded in for 40% smaller IM1 contact area, allowing for a cell silicon footprint benefit of up to 20%. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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