Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC
| Autor: | Debbie Marr, Sheffield David B, Jaewoong Sim, Eriko Nurvitadhi, Ganesh Venkatesh, Asit K. Mishra |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Artificial neural network
Xeon business.industry Computer science Deep learning 020208 electrical & electronic engineering 02 engineering and technology Parallel computing 020202 computer hardware & architecture CUDA Application-specific integrated circuit 0202 electrical engineering electronic engineering information engineering Hardware acceleration System on a chip Artificial intelligence business Field-programmable gate array Computer hardware |
| Zdroj: | FPT |
| DOI: | 10.1109/fpt.2016.7929192 |
| Popis: | Deep neural networks (DNNs) are widely used in data analytics, since they deliver state-of-the-art accuracies. Binarized neural networks (BNNs) are recently proposed optimized variant of DNNs. BNNs constraint network weight and/or neuron value to either +1 or −1, which is representable in 1 bit. This leads to dramatic algorithm efficiency improvement, due to reduction in the memory and computational demands. This paper evaluates the opportunity to further improve the execution efficiency of BNNs through hardware acceleration. We first proposed a BNN hardware accelerator design. Then, we implemented the proposed accelerator on Aria 10 FPGA as well as 14-nm ASIC, and compared them against optimized software on Xeon server CPU, Nvidia Titan X server GPU, and Nvidia TX1 mobile GPU. Our evaluation shows that FPGA provides superior efficiency over CPU and GPU. Even though CPU and GPU offer high peak theoretical performance, they are not as efficiently utilized since BNNs rely on binarized bit-level operations that are better suited for custom hardware. Finally, even though ASIC is still more efficient, FPGA can provide orders of magnitudes in efficiency improvements over software, without having to lock into a fixed ASIC solution. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|