A sub-0.1 μm gate length CMOS technology for high performance (1.5 V) and low power (1.0 V)

Autor:	M. Redder, Q.Z. Hong, M. Nandakumar, S. Aur, J.C. Hu, I.-C. Chen
Rok vydání:	2002
Předmět:	Physics CMOS business.industry Electrical engineering Gate length Analytical chemistry Short-channel effect Rapid thermal annealing business Cmos process NMOS logic PMOS logic
Zdroj:	International Electron Devices Meeting. Technical Digest.
DOI:	10.1109/iedm.1996.554046
Popis:	A high performance 1.5 V, sub-0.18 /spl mu/m (physical) gate length CMOS technology and extension to a 1.0 V technology for low power applications is described. nMOS with nominal I/sub drive/=740, 580, and 380 /spl mu/m are achieved for V/sub DD/=1.8, 1.5, and 1.0 V at accumulation t/sub ox/=36 A (from C-V at V/sub gb/=-3 V). pMOS with nominal I/sub drive/ of 300 (1.8 V), 222 (1.5 V), and 140 /spl mu/A//spl mu/m (1.0 V) are achieved. Target L/sub g//sup min/ (minimum gate length)=0.15-0.16 /spl mu/m. Drive currents are comparable to a recently reported 0.08 /spl mu/m CMOS process. Low nMOS R/sub SD/
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::91307a1416959e961b425626326e9545 https://doi.org/10.1109/iedm.1996.554046 Zobrazit plný text záznamu