| Popis: |
CMOS scaling is increasingly being hindered by the rapid rise in the transistor's parasitic resistance as the source/drain (s/d) contact area is reduced. Increased dopant activation at the s/d is essential for reducing the contact resistivity but is limited by solid solubility, electrical deactivation, segregation at interfaces and by temperature limits imposed by process integration requirements. A recent study of millisecond annealing (MSA) of high-dose ion implants of As and P in preamorphized Si suggests paths for electrical activation improvements even for peak temperatures |
