Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability?

Autor:	Jeff Siddiqui, Scott K. Pozder, Gaddi Haase, Karsten Beckmann, P. Justison, Tom Kopley, Martin Anselm, Matt Ring
Rok vydání:	2017
Předmět:	Wire bonding Semiconductor Reliability (semiconductor) business.industry Computer science Semiconductor device modeling Wafer Fracture mechanics business Reliability engineering
Zdroj:	2017 IEEE International Integrated Reliability Workshop (IIRW).
DOI:	10.1109/iirw.2017.8361249
Popis:	Are the fields of fracture mechanics, rheology, etc. good enough to address issues In package reliability? No: JEDEC specs all based on DIP wirebond packages. Are we using results from these fields enough or most effectively? Not addressed. Biggest difference with wafer reliability is stressors on chip are local (E-field, temperature), which stressors in a package are mechanical stress, which is resultant of the entire package materials' CTE.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::904e2d75c90333ecfc4c9f8212d1281f https://doi.org/10.1109/iirw.2017.8361249 Zobrazit plný text záznamu