A Low-Flicker Noise Gate-Controlled Lateral–Vertical Bipolar Junction Transistor Array With 55-nm CMOS Technology
| Autor: | Shuo-Mao Chen, Feng-Renn Juang, Hua-Chou Tseng, Chih-Ping Chao, Chia-Chung Chen, Sally Liu, Yean-Kuen Fang, Chin-Wei Kuo |
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| Rok vydání: | 2011 |
| Předmět: |
Engineering
Heterostructure-emitter bipolar transistor business.industry Heterojunction bipolar transistor Bipolar junction transistor Electrical engineering Integrated circuit Noise (electronics) Electronic Optical and Magnetic Materials law.invention CMOS law Flicker noise Electrical and Electronic Engineering business NMOS logic |
| Zdroj: | IEEE Transactions on Electron Devices. 58:3276-3282 |
| ISSN: | 1557-9646 0018-9383 |
| Popis: | The low-flicker noise (1/f noise) gate-controlled lateral-vertical bipolar junction transistor array (GC-LV-BJTA) is developed with a foundry's 55-nm CMOS technology for low-noise and low-power RF circuit applications. The GC-LV-BJTA is formed by paralleling some unit cells into an array structure for sharing adjacent collectors and bases, thus minimizing the total area. Many efforts, including the use of a deep n-well, a novel layout, an optimized emitter perimeter/area ratio, and a negatively biased gate, have been implemented to suppress the noise level and enhance the current gain. As a result, the GC-LV-BJTA, consisting of 16 unit cells with a 0.16-μm gate length, achieves a high gain of 85.7 with available low 1/f noise level, as compared with the nMOS or SiGe HBT. |
| Databáze: | OpenAIRE |
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