Performance features of the PA7100 microprocessor
| Autor: | J. Yetter, T. Asprey, B. Weiner, R. Mason, E. DeLano, G.S. Averill |
|---|---|
| Rok vydání: | 1993 |
| Předmět: |
Coprocessor
Reduced instruction set computing CPU cache Computer science business.industry Pipeline (computing) Translation lookaside buffer Multiprocessing Virtual address space Hardware and Architecture Superscalar Central processing unit Cache Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Instruction cycle business Software Computer hardware x87 |
| Zdroj: | IEEE Micro. 13:22-35 |
| ISSN: | 0272-1732 |
| DOI: | 10.1109/40.216746 |
| Popis: | The PA7100 CPU, the first precision-architecture, reduced-instruction-set-computer (PA-RISC) architecture implementation to combine an integer core and floating-point coprocessor into a single-chip format, is described. It incorporates superscalar execution and supports clock rates of up to 100 MHz in standard 0.8- mu m CMOS. Features such as a flexible primary cache organization and multiprocessing capability allow the device to be scaled to a variety of system applications, price ranges, and performance levels. The microprocessor instruction execution pipeline, cache design, translation look-aside buffer (TLB) for virtual address translation, floating-point unit, and system interface bus are discussed. The design, test, and verification methods used in the development of the PA7100 are reviewed. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|