Multilevel interconnections for wafer scale integration
| Autor: | R. O. Carlson, C. A. Neugebauer, A. S. Bergendahl, J. F. McDonald, Andrew J. Steckl |
|---|---|
| Rok vydání: | 1986 |
| Předmět: |
education.field_of_study
Wafer-scale integration Fabrication Materials science business.industry Population Nanotechnology Hardware_PERFORMANCEANDRELIABILITY Surfaces and Interfaces Integrated circuit Condensed Matter Physics Wafer backgrinding Surfaces Coatings and Films law.invention Die preparation Etching (microfabrication) law Hardware_INTEGRATEDCIRCUITS Optoelectronics Wafer business education |
| Zdroj: | Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films. 4:3127-3138 |
| ISSN: | 1520-8559 0734-2101 |
| Popis: | Multilevel interconnections (MLIC) are the key to successful wafer scale integration (WSI). In this paper, we present a review of various approaches used in the implementation in MLIC to both monolithic WSI and wafer scale hybrid packaging. Electrical interconnections using both thin (micron dimensions) and thick (tens of microns dimensions) dielectric and metal films are discussed from a performance standpoint. The advantages of the thick film approach for realizing transmission line performance is indicated. Techniques for implementing thick electrical interconnections such as plate‐up, via etching and lift‐off, are described. This treatment includes silicon‐die‐on‐wafer, silicon‐die‐on‐ceramic, and GaAs‐on‐silicon wafer hybrids. Fabrication approaches which have been explored by several research groups are compared. Some projections concerning yield of the wafer interconnections are calculated. Finally, a brief examination of some potential approaches to three‐dimensional stacking of wafers is made, including two‐sided population of wafers. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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