A multi-bit sigma-delta ADC for multi-mode receivers

Autor:	M.R. Miller, C.S. Petrie
Rok vydání:	2003
Předmět:	Physics Spurious-free dynamic range Offset (computer science) CMOS business.industry Low-power electronics Electrical engineering Electronic engineering Linearity business Delta-sigma modulation Noise shaping Electronic circuit
Zdroj:	Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).
Popis:	A 2.7-volt /spl Sigma//spl Delta/ modulator with a 6-bit quantizer is fabricated in a 0.18 /spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching and quantizer offset chopping to attain high linearity over a wide bandwidth. The circuit achieves 95 dB peak SFDR and 77 dB SNR over a 625 kHz bandwidth and consumes 30 mW at a sampling frequency of 23 MHz. Further, it achieves 70 dB SNR over a 1.92 MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::8e2f7c268de77c78f931e5991b6665e8 https://doi.org/10.1109/cicc.2002.1012795 Zobrazit plný text záznamu