Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing

Autor:	Sushanta K. Mandal, L. B. Omprakash, B. S. Patro, Suryasnata Tripathy
Rok vydání:	2015
Předmět:	Digital signal processor Adder Computer science Transistor law.invention Computer architecture law Logic gate Electronic engineering Multiplier (economics) Overall performance Hardware_ARITHMETICANDLOGICSTRUCTURES Cadence Cmos process
Zdroj:	2015 International Conference on Communication, Information & Computing Technology (ICCICT).
DOI:	10.1109/iccict.2015.7045662
Popis:	Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low power designs are realized in 45 nm CMOS Process technology using Cadence EDA tool.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::8dc85e2d68fb97d283c715e08accafb4 https://doi.org/10.1109/iccict.2015.7045662 Zobrazit plný text záznamu