16.9 4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur
| Autor: | Brian Shelly, Michael F. Keaveney, Stephen Brookes, Patrick Griffin, Sanganagouda Patil, James Breslin, Stefano Tulisi, Yann Donnelly, Ciaran Curtin, Michael Peter Kennedy |
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| Rok vydání: | 2019 |
| Předmět: |
Loop (topology)
Frequency synthesizer Physics Discrete mathematics Phase-locked loop Voltage-controlled oscillator Quantization (signal processing) 020208 electrical & electronic engineering 0202 electrical engineering electronic engineering information engineering Sigma Spurious tone 02 engineering and technology Noise shaping |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2019.8662327 |
| Popis: | The instantaneous divide value of the multimodulus divider in the feedback path of a fractional-N PLL is determined by a divider controller, which is usually implemented as a digital delta-sigma modulator $(\mathrm (D)\Delta \Sigma \mathrm (M))$. A disadvantage of the fractional-N PLL is the presence of fractional spurs, which result from interaction between the signal introduced by the $(\mathrm (D)\Delta \Sigma \mathrm (M))$ and nonlinearities in the loop. When fractional spurs at frequencies close to integer boundaries lie inside the loop bandwidth, they cannot be attenuated by filtering. The Successive Requantizer (SR) is an alternative to the $(\mathrm (D)\Delta \Sigma \mathrm (M))$-based divider controller, which randomizes the quantization process more effectively than $(\mathrm (D)\Delta \Sigma \mathrm (M))$. Wang et al. reported a worst-case in-band fractional spur of -64dBc in a 2.4GHz charge-pump PLL [1]. Liang and Wang reported a -70dBc worst-case fractional spur in a 2GHz analog PLL with a hybrid VCO and $(\mathrm (D)\Delta \Sigma \mathrm (M))$-based divider controller [2]. Familier and Galton improved the performance of the SR by implementing higher-order noise shaping. They achieved a worst-case fractional spur of -72dBc in a 3.3GHz analog PLL with a third-order SR [3]. The SR quantizes the frequency-control word one bit at a time, and, therefore, requires n stages in the case of an n-bit modulus. Thirunarayanan et al. implemented a hybrid MASH-SR divider-controller structure using four SR quantization blocks [4]. The divider-controller architecture described in this paper enables a 4.48GHz analog PLL to exhibit an in-band fractional spur of -80dBc and a -145dBc reference spur. It comprises a conventional MASH $(\mathrm (D)\Delta \Sigma \mathrm (M))$ followed by a programmable Probability Mass Redistributor (PMR). The PMR requantizes the output of the $(\mathrm (D)\Delta \Sigma \mathrm (M))$ and redistributes its samples in such a way that the in-band spurs are reduced by 7dB compared to the $(\mathrm (D)\Delta \Sigma \mathrm (M))$ alone. |
| Databáze: | OpenAIRE |
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