Area efficient run time reconfigurable architecture for double precision multiplier
| Autor: | Shanmugapriyan S, Sivanandam K |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Multiplication algorithm
Quadruple-precision floating-point format Computer science Arbitrary-precision arithmetic Floating-point unit Double-precision floating-point format Parallel computing Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic Extended precision Single-precision floating-point format Half-precision floating-point format |
| Zdroj: | 2015 IEEE 9th International Conference on Intelligent Systems and Control (ISCO). |
| DOI: | 10.1109/isco.2015.7282355 |
| Popis: | In many application Floating point Arithmetic is basic building blocks such as Scientific, digital signal processing and numeric. In this Floating point Arithmetic, Multiplication is most commonly used method. This multipliers are going to discussing about the double precision multiplier. This double precision operation is performed in the form of IEEE-754 FP (floating point) standard format. The first architecture is the novel truncated block multiplication, with one unit in the last place (ULP) precision from IEEE-754 FP standard format. The second architecture is used to regain the lost of accuracy from the first design with some extra hardware logic. The third architecture is used to perform either single precision or double precision. The Vedic multiplication algorithm is used in all the architecture for the purpose of multiplication process. |
| Databáze: | OpenAIRE |
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