HARDWARE IMPLEMENTATION AND VERIFICATION OF FIR FILTER UTILIZING M-BIT PDA
| Autor: | Hsing-Chen Lin, Shu-Ming Chang, Shiann Shiun Jeng, Chun-Chyuan Chen |
|---|---|
| Rok vydání: | 2010 |
| Předmět: |
Adder
Finite impulse response business.industry Computer science Clock rate General Medicine Phase-locked loop Bit (horse) Hardware and Architecture Embedded system Stratix Multiplier (economics) Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business Field-programmable gate array Computer hardware |
| Zdroj: | Journal of Circuits, Systems and Computers. 19:503-517 |
| ISSN: | 1793-6454 0218-1266 |
| DOI: | 10.1142/s0218126610006207 |
| Popis: | An efficient architecture for a FPGA symmetry FIR filter is proposed that employs the M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed ROM to eliminate a large amount of multiplications. Altera Stratix II EP2S60 is used as a target device to implement the M-bit PDA. The hardware implementation requires 936 adaptive look-up tables (ALUTs), 888 registers, 1 PLL, 40960 memory bits for the FIR filter implementation with the M-bit PDA (in this case M = 2). Additionally, the maximum clock rate for this implementation can be achieved up to 155.36 MHz. In comparison with the parallel multiplier/adder cell (MAC) and serial distributed arithmetic (SDA), the proposed architecture consumes a smaller area and operates with a higher speed due to omitting the multipliers. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|