Logic synthesis in a CAE design environment-a tutorial
| Autor: | R. Sullivan, R. McCann, J. Southard, O. Levia |
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| Rok vydání: | 2002 |
| Předmět: |
User information
Computer science Programming language media_common.quotation_subject Process (computing) Process design computer.software_genre Logic synthesis Logic gate High-level synthesis Function (engineering) Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer Hardware_LOGICDESIGN Logic optimization media_common |
| Zdroj: | Third Annual IEEE Proceedings on ASIC Seminar and Exhibit. |
| DOI: | 10.1109/asic.1990.186079 |
| Popis: | Logic synthesis is defined with respect to its input and output, and the flow of data and control in a logic synthesis system is described. Each individual step in such a system is described in detail and the function of each such step is defined. The transformation that the design representation goes through is defined and it is shown how user information and control serves to direct the synthesis process. Emphasis is placed on the input to the synthesis process (the design representation), the control a user has over the synthesis process, and how technology-specific information (library) is used in such a process. Examples from an existing logic synthesis system are used to clarify these points. > |
| Databáze: | OpenAIRE |
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