| Popis: |
The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix. |
