Estimation and Analysis of Power Loss in a Reduced Switches Count H-Bridge Multilevel Inverter
| Autor: | Almachius Kahwa, Hidemine Obara, Yasutaka Fujimoto |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Computer science
business.industry 020208 electrical & electronic engineering Electrical engineering 020206 networking & telecommunications Topology (electrical circuits) 02 engineering and technology Converters H bridge Network topology Power (physics) Power electronics 0202 electrical engineering electronic engineering information engineering Power semiconductor device business Diode |
| Zdroj: | ICM |
| DOI: | 10.1109/icmech.2019.8722859 |
| Popis: | In order to achieve higher efficiency operation of power electronics devices (power converters), conduction and switching losses have to be reduced. Due to its modest circuit, few power devices and high efficiency, the H-bridge multilevel inverter has proven itself superior even among the most popular multilevel inverter topologies, even though its efficiency is greatly affected by the switching and conduction losses that mostly occur in main switching power devices and anti-parallel diodes. An alternative to minimize these losses is to reduce the number of switching power devices. This paper presents a theoretical analysis and simulation of power losses in a 5-level H-bridge multilevel inverter with reduced number of main switching devices. A comparative discussion of the theoretical and simulated power loss values is addressed based on how the reduction of power switches contributed to the decrease of conduction and switching losses. A 5-level H-bridge multilevel inverter based on 5-kHz switching frequency was simulated in PSIM under thermal operation to mimic actual working conditions of power switching devices and illustrate their respective losses. |
| Databáze: | OpenAIRE |
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