Performance modeling and analysis of parallel packet switches with PIAO queues
| Autor: | Chin-Chi Wu, Chia-Lung Liu, Woei Lin, Ding-Jyh Tsaur |
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| Rok vydání: | 2007 |
| Předmět: | |
| Zdroj: | Journal of the Chinese Institute of Engineers. 30:689-701 |
| ISSN: | 2158-7299 0253-3839 |
| DOI: | 10.1080/02533839.2007.9671295 |
| Popis: | When buffer resources are deployed in the switch, shared‐memory based packet switches are known to supply the best possible performance for bursty data traffic in networks and the Internet. Nevertheless, scaling of shared‐memory packet switches to larger sizes has been limited and then packets can not be processed in a high speed network, chiefly because of the physical restrictions imposed by the memory operation rate and the centralized strategy for switching functions in shared‐memory switches. In this investigation, a scalable switch for a high speed network, which is called the parallel packet switch (PPS), is studied to overcome these constraints. The PPS comprises multiple packet switches operating independently and in parallel. The PPS class is characterized by the deployment of parallel center‐stage switches with memory buffers running slower than the external line rate. Each lower speed packet switch operates at a fraction of the external line rate R. For example, each packet switch can... |
| Databáze: | OpenAIRE |
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