Architecture design to optimize multipliers in FPGAs based on Maya multiplying method
| Autor: | Jorge Rivera Dominguez, Edwin Christian Becerra Alvarez, Susana Ortega Cisneros, Juan José Raygoza Panduro, Fabian Venegas Siordia |
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| Rok vydání: | 2016 |
| Předmět: |
business.industry
Computer science Binary multiplier Parallel computing Architecture design Computer Science::Hardware Architecture Parallel processing (DSP implementation) Parallelism (grammar) Multiplication Hardware_ARITHMETICANDLOGICSTRUCTURES Architecture Field-programmable gate array business Digital signal processing |
| Zdroj: | 2016 IEEE Central America and Panama Student Conference (CONESCAPAN). |
| Popis: | The Mayan binary multiplier is an architecture to simplify and optimize the multiplication implemented in FPGAs. This architecture is based on the Maya multiplication method or Tzeltal. The architecture takes advantage of the parallelism of FPGAs grouping multipliers for generating the partial products. The multiplication is accelerated by decreasing the number of sums to be performed. This new approach provides properties that improve arithmetic calculations. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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