A 5/10 Gb/s Dual-Mode NRZ/PAM4 CDR in 65-nm CMOS
| Autor: | Guopei Chen, Baoyong Chi, Luqiang Duan, Zheng Song, Ruichang Ma, Mengdi Cao |
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| Rok vydání: | 2019 |
| Předmět: |
Physics
business.industry 020208 electrical & electronic engineering 02 engineering and technology Signal QAM CMOS Pulse-amplitude modulation 0202 electrical engineering electronic engineering information engineering Optoelectronics Frequency offset business Quadrature amplitude modulation Phase-shift keying Jitter |
| Zdroj: | 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). |
| DOI: | 10.1109/edssc.2019.8754128 |
| Popis: | A dual-mode clock and data recovery (CDR) circuit based on phase interpolator (PI) in 65nm CMOS is presented. CDR can recover clock from quadrature phase shift keying (QPSK) modulated signal in non-to-zero (NRZ) mode, and 16 quadrature amplitude modulation (QAM) signal in 4 pulse amplitude modulation (PAM4) mode. An adaptive threshold voltage loop for PAM4 signal is proposed. Simulation results show that CDR can track maximum ± 1000 ppm frequency offset between transmitter and receiver in two modes, and the jitter of the locked clock is 45.2ps in NRZ mode and 47.8ps in PAM4 mode, respectively. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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