ASIC realization and performance evaluation of 64×64 bit high speed multiplier in CMOS 45nm using Wallace Tree
| Autor: | S K PradeepKumar, S V Harshitha, K R Ankitha, K Nandini, T G Chaithra |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
021110 strategic
defence & security studies Adder business.industry Computer science 0211 other engineering and technologies 02 engineering and technology Wallace tree Application-specific integrated circuit CMOS Carry-select adder Multiplier (economics) Carry-save adder Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Computer hardware |
| Zdroj: | 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). |
| DOI: | 10.1109/rteict.2017.8256771 |
| Popis: | Core data path element in any processing system is multiplier which determines overall processing unit performance, particularly related to DSP applications. Any performance improvements in multiplier unit will boost the potential of such system. A 64×64 Bit high speed multiplier is realized in ASIC Digital flow (RTL to GDS-II) with performance evaluation using Cadence EDA. Proposed multiplier designed with Wallace structure with carry save adder and carry select adder for optimizing speed criteria. Wallace reduction becomes more complex and irregular in structure for larger operand width which consumes more design time. Proposed method reduces the design time with regularity. The 45 nm CMOS technology is used for implementation and results are compared for delay, silicon area and dynamic power dissipation with other existing methods. |
| Databáze: | OpenAIRE |
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