| Autor: |
Chun-Chia Chen, Ping Chao, Huaide Wang, Min-Hao Chiu, Chia-Yun Cheng, Chang-Lin Hsieh, Hue-Min Lin, Ryan Yeh, Chih-Ming Wang, Hsiu-Yi Lin, Chung-Hung Tsai, Ted Chuang, Yung-Chang Chang, Chi-cheng Ju, Tsu-Ming Liu, Sheng-Jen Wang, Brian Liu, Meng-Jye Hu |
| Rok vydání: |
2014 |
| Předmět: |
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| Zdroj: |
VLSIC |
| DOI: |
10.1109/vlsic.2014.6858389 |
| Popis: |
A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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