Impact of process parameters on circuit performance for the 32nm technology node
| Autor: | B. Blampey, Bernard Flechet, M. Sellier, M. Gallitre, L. Guibe, Vincent Arnal, Cedric Bermond, Alexis Farcy, Joaquim Torres |
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| Rok vydání: | 2007 |
| Předmět: |
Limiting factor
Interconnection Computer science media_common.quotation_subject Process (computing) Integrated circuit Condensed Matter Physics Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials law.invention Stack (abstract data type) law Electronic engineering Node (circuits) Time domain Electrical and Electronic Engineering Function (engineering) media_common |
| Zdroj: | Microelectronic Engineering. 84:2738-2743 |
| ISSN: | 0167-9317 |
| Popis: | As IC dimensions scale down to the 32nm technology node, interconnect is more than ever the most limiting factor affecting overall circuit performance. The influence of all involved process parameters were studied as a function of target application through electromagnetic and time domain simulations, and compared to the impact of driver characteristics. As a result, an optimization of the BEOL stack was performed to propose process and material recommendations meeting electrical specifications for most circuit applications. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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