A Transimpedance-to-Noise Optimized Analog Front-End With High PSRR for Pulsed ToF Lidar Receivers
| Autor: | Ehsan Afshari, Bahareh Hadidian, Keshu Zhang, Farzad Khoeini |
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| Rok vydání: | 2021 |
| Předmět: | |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers. 68:3642-3655 |
| ISSN: | 1558-0806 1549-8328 |
| DOI: | 10.1109/tcsi.2021.3089098 |
| Popis: | This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB $\boldsymbol {\Omega }$ transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a $0.11\, \boldsymbol {\mu }\text{m}$ CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving $50 \boldsymbol {\Omega } $ loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 $\boldsymbol {\mu }\text{m}\,\,\boldsymbol {\times } 110\,\,\boldsymbol {\mu }\text{m}$ in area. |
| Databáze: | OpenAIRE |
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