50Gb/s 3.3V logic ICs in InP-HBT technology

Autor:	R. Thiagarajah, R. Coccioli, J. Rogers, K. Nary, E. Arnold, S. Yinger, T.P.E. Broekaert, N. Srivastava, J. Sanders, P. van der Wagt, S. Zheng
Rok vydání:	2004
Předmět:	Engineering OR gate Pass transistor logic business.industry Heterojunction bipolar transistor Frequency multiplier Rise time Logic gate Electrical engineering Phase margin business Sensitivity (electronics)
Zdroj:	2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
DOI:	10.1109/vlsic.2004.1346604
Popis:	50Gb/s 3.3V InP-HBT logic ICs with 6ps rise time and 1200mVpp output swing include: D-flip-flop, double-edge triggered flip-flop, dividers, a frequency doubler, XOR/OR gates, and a 1:2 fanout buffer. The DFF has 3ps/sub pp/ deterministic and 270deg phase margin, and 12mV/sub pp/ sensitivity at 40Gb/s and 10/sup -12/ BER. The ICs dissipate 480-840mW in 1mm/sup 2/.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::8a2234dc8eccc46d79fb78f9fb2fe08b https://doi.org/10.1109/vlsic.2004.1346604 Zobrazit plný text záznamu