Application of synchrotron x-ray lithography to fabricate fully scaled 0.5 μm complementary metal–oxide semiconductor devices and circuits

Autor: L. K. Wang, H. Voelker, O. Vladimirsky, David E. Seeger, B. Hill, E. Petrillo, J. P. Silverman, C. Wasik, Raul E. Acosta, Robert P. Rippstein, R. Viswanathan, Karen Petrillo, John Michael Warlaumont, K. Kwietniak, D. Katcoff, R. Devenuto, Inna V. Babich, V. DiMilia, L. C. Hsia, S. Brodsky, A. D. Wilson
Rok vydání: 1989
Předmět:
Zdroj: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 7:1662
ISSN: 0734-211X
DOI: 10.1116/1.584477
Popis: High performance fully scaled 0.5 μm complementary metal–oxide semiconductors very large scale integrated (CMOS VLSI) circuits have been fabricated using synchrotron x‐ray lithography technology. X‐ray lithography is employed at all levels to attain a minimum feature size of 0.5 μm. The wafer exposures are done at the VUV storage ring from the National Synchrotron Light Source, Brookhaven National Laboratory. A stepper built at IBM Yorktown Heights is used at the beamline to perform the wafer exposures. All the lithography levels are aligned to the prefabricated 0.5 μm deep silicon trench zero level with an overlay less than 0.1 μm (1σ) between levels. Single level resists (both positive and negative) are used throughout the entire CMOS process. Linewidth control better than 0.01 μm and alignment tolerance less than 0.10 μm are accomplished. The patterning of this x‐ray lithography mask is accomplished through a vector scan electron beam direct writing system. Masks made of boron doped silicon membranes w...
Databáze: OpenAIRE