| Autor: |
Donald W. Johnson, Bin-Hong Tsai |
| Rok vydání: |
2011 |
| Předmět: |
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| Zdroj: |
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2011:000635-000665 |
| ISSN: |
2380-4491 |
| Popis: |
The focus of this presentation is on the use of SUEX epoxy Thick Dry Film Sheets (TDFS) as a photoimagable dielectric layer in fan-in, fan-out and e-WLP applications. The sheets can be laminated over severe topography from under 2 μm to over 200 μm in height yielding void free coatings with 100% planarization over the entire substrate. The TDFS are available in a range of thicknesses and wafer or panel sizes. This new material is prepared under a highly controlled solvent-less process, which provides uniform coatings between two throw-away layers of protective polyester film. SUEX sheets of 100 μm thickness have been vacuum laminated in an isothermal process at 60–80°C over 180 μm high, 2mm X 2mm device chips mounted onto a silicon carrier wafer. Process optimization studies were run to determine the desired chamber vacuum, chuck temperature, lamination pressure and lamination time for optimal performance. The entire lamination process has a cycle time of about 10min. Using a vacuum laminator we have been able to obtain totally void-free coatings over 2 to 5 μm high bonding pads and buss lines at the silicon surface with a resist thickness of 205 μm over the trench and 25 μm thickness over the back of the chip with 100% planarization over the surface interface. Exposures on a contact aligner have yielded nominal 50 μm diameter via holes through the resist film to the contact pads at the bottom of the trench. Excellent adhesion to all surfaces on both the carrier wafer and the device chip has been obtained without any delamination or crack formation. Additional work to be presented will demonstrate the filling of the vias with electroplated copper to form interconnects the interconnects to for connection to bonding pads on the fan-out package surface. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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