An S/H circuit with parasitics optimized for IF-sampling
| Autor: | Li Weitao, Wang Zhi-jun, Li Fule, Wang Zhihua, Jia Wen, Yue Shigang, Zheng Xuqiang |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
Spurious-free dynamic range Pipeline (computing) Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology law.invention Parasitic capacitance Linearization law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Materials Chemistry Electronic engineering Parasitic extraction Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business.industry 020208 electrical & electronic engineering Transistor Electrical engineering Sampling (statistics) Linearity Condensed Matter Physics 020202 computer hardware & architecture Electronic Optical and Magnetic Materials business |
| Zdroj: | Journal of Semiconductors. 37:065005 |
| ISSN: | 1674-4926 |
| Popis: | An IF-sampling S/H is presented, which adopts a flip-around structure, bottom-plate sampling technique and improved input bootstrapped switches. To achieve high sampling linearity over a wide input frequency range, the floating well technique is utilized to optimize the input switches. Besides, techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance. The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit, 250 MS/s pipeline ADC. For 30 MHz input, the measured SFDR/SNDR of the ADC is 94.7 dB/68. 5dB, which can remain over 84.3 dB/65.4 dB for input frequency up to 400 MHz. The ADC presents excellent dynamic performance at high input frequency, which is mainly attributed to the parasitics optimized S/H circuit. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|