74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations
| Autor: | Pang-Yen Lou, Chua-Chin Wang, Tsung-Yi Tsai, Hsiang-Yu Shih |
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| Rok vydání: | 2019 |
| Předmět: |
Read-only memory
Spurious-free dynamic range Dynamic range Pipeline (computing) Clock rate dBc 02 engineering and technology Topology 020202 computer hardware & architecture CMOS Hardware and Architecture Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Software Mathematics Interpolation |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27:2464-2468 |
| ISSN: | 1557-9999 1063-8210 |
| Popis: | In this brief, a four-stage pipeline read only memory (ROM)-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed. To attain higher spurious-free dynamic range (SFDR) and faster clock rate, the hardware cost and delay using different segments with various interpolation equations are analyzed systematically to explore the optimal solution. The second-order parabolic equations with proper coefficients and factorized operation orders based on optimized hardware cost and delay are finally utilized to enhance SFDR. The proposed design is demonstrated by the physical implementation using the TSMC 0.18- $\rm {\mu }\text{m}$ CMOS technology cell library and on-silicon measurements, where the maximum SFDR is 74 dBc, 0.018-mW/MHz power dissipation, and the maximal clock frequency is 71.9 MHz. |
| Databáze: | OpenAIRE |
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