Streaming implementation of a sequential decompression algorithm on an FPGA

Autor:	Gaurav Mittal, Prithviraj Banerjee, David Zaretsky
Rok vydání:	2009
Předmět:	Speedup Computer science business.industry Pentium computer.software_genre Reconfigurable computing Software Embedded system VHDL Operating system Software design System on a chip Field-programmable gate array business computer Algorithm computer.programming_language
Zdroj:	FPGA
DOI:	10.1145/1508128.1508195
Popis:	This paper describes an FPGA based implementation of a real time compression algorithm used in transactions between financial institutions such as exchanges and trading houses. FIX is a protocol that has gained widespread popularity for exchanging financial information such as stock prices and purchases over the Internet. If a financial trader can speed up the processing of these protocols, he can make significant financial profits by buying or selling stocks when there is a lot of variability in the share prices. Our methodology tries to recognize and exploit streaming characteristics of the software design in order to implement a pipelined parallel processing system in reconfigurable hardware. It introduces the concept of caches to keep stream pipelines filled more often. The system implemented on a Xilinx Virtex5 LX110T FPGA shows a 17x speedup in throughput over a software implementation running on a dual core Intel Pentium workstation. These techniques are being developed as part of commercial compiler project to automatically translate software binaries to streaming RTL VHDL systems.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::89a8c49adf25313b232a031718d80480 https://doi.org/10.1145/1508128.1508195 Zobrazit plný text záznamu