| Popis: |
R&D on transistor fabrication and scaling for current and future technology nodes involves various 3D-device architectures like the established finFET (fin “Field Effect Transistor”), and newer architectures like GAA (Gate All Around) which may include VFET (vertical FET), CFET (complimentary FET), etc. These new architectures are being investigated as potential solutions to enable further CMOS area and performance scaling and continue Moore’s law. Typically node to node area scaling is achieved through pitch reduction of critical layers such as contacted poly pitch (CPP) and fin pitch in FEOL, and Mx pitch in the BEOL. For such advanced nodes, at the device level, the CPP reduction translates to a stronger drive for shorter gate length (Lg) and so, for improved electrostatics control (Ion, Ioff, Tinv, etc.). Integration schemes for such advanced 3D architectures must deliver excellent process control and uniformity, especially for critical device features such as gate length and channel dimensions, and demand self-aligned multi-patterning schemes to address edge-placement accuracy, overlay, multiple mask sets, etc. A frequently encountered etch step in such integration schemes is the trimming of Si features made of mono, polycrystalline, or amorphous Si. Some key applications are listed here: fin trimming for (1) lateral transport finFET and for (2) vertical transport VFET, (3) final gate trim for lateral transport finFET, GAA/CFET, etc. (4) amorphous gate mandrel trim for lateral transport FETs (multi-patterning). |
