Dipole-induced gate leakage reduction in scaled MOSFETs with a highly doped polysilicon/nitrided oxide gate stack
| Autor: | Ukjin Jung, Young Gon Lee, James Walter Blatchford, Brian K. Kirkpatrick, Hiroaki Niimi, Younggy Kim, Seung-Chul Song, Jin Ju Kim, Byoung Hun Lee |
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| Rok vydání: | 2015 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Materials science business.industry Polysilicon depletion effect Gate dielectric Time-dependent gate oxide breakdown Equivalent oxide thickness Hardware_PERFORMANCEANDRELIABILITY Condensed Matter Physics Capacitance Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials Hardware_GENERAL Gate oxide Hardware_INTEGRATEDCIRCUITS Optoelectronics Electrical and Electronic Engineering business Metal gate Hardware_LOGICDESIGN Leakage (electronics) |
| Zdroj: | Microelectronic Engineering. 142:1-6 |
| ISSN: | 0167-9317 |
| Popis: | Gate leakage current is reduced up to 24% using a highly doped polysilicon gate/nitrided oxide gate stack. Interestingly, various factors that could affect the gate leakage current such as equivalent oxide thickness (EOT), overlap capacitance, gate dielectric reliability and sub-threshold voltage were found to be unrelated to the reduction in leakage current. Instead, an additional band offset due to an interfacial dipole at the highly doped polysilicon gate and nitrided oxide interface is proposed to explain the anti-intuitive leakage current reduction. This result implies that there is an optimal gate doping condition that will minimize the leakage current accounting a trade-off between the effect of the interfacial dipole and reliability. |
| Databáze: | OpenAIRE |
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