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As on-chip interconnect sizes continue to shrink to address the increased device density needs at 7 nm nodes and beyond, copper interconnects start showing an increase of electrical resistivity compared to bulk copper due to the scaling effect. Recent development strategies have implemented cobalt as a favorable short electron mean-free path interconnect metal for contact interconnect levels already at 10 nm node and is also considered for use as a conductor in higher metal levels. CVD cobalt has been considered, but appears too costly and time consuming for high volume manufacturing. Electro chemical deposition (ECD) of cobalt is deemed the most promising candidate, and has already been implemented into manufacturing lines of the most advanced node chip manufacturers. Unlike electrolytic Cu bottom-up fill, which usually requires both an accelerator and a suppressor, the electrolytic Co bottom-up fill process in many reported cases only includes one single suppressor in the plating bath. The filling mechanism of Co is therefore very different from Cu. In this work, we propose a hydrogen reduction-induced deactivation mechanism for cobalt bottom-up filling. The plating bath employs a single additive - Atomplate Co Suppressor XF. Cyclic Voltammagram (CV) shows it suppresses Co plating in the forward (negative) scan, while suppression is lost in the reverse (positive) scan (fig. 1, upper panel). The loss of suppression, or suppressor deactivation, is due to hydrogen reduction. This suppressor can be reduced by hydrogen that is simultaneously generated during plating by electrolysis. The current efficiency measurement suggests that hydrogen is produced throughout the tested potential range. The current efficiency increases with current density, although the generated amount of hydrogen is larger at higher current density. The amount of activated / deactivated Atomplate Co Suppressor XF at the surface is dependent on the concentration of protons (pH), concentration of additive, and the rotation rate. On the patterned wafer, the local current is governed by the amount of activated and deactivated additive. At the beginning of the plating, more hydrogen is generated in the bottom of the feature due to higher surface-to-volume ratio. While more hydrogen in the bottom is generated, more suppressor is deactivated and the current at the bottom becomes larger than that on the top. The bottom-up filling is then initiated as a result of this surface-to-volume effect. Once the bottom-up filling is initiated, the higher current at the bottom of the feature generates more hydrogen as suggested by the current efficiency measurement. Hence the bottom-up filling is further enhanced due to this current density effect. In the later stage of the filling, the surface-to-volume effect diminishes, however the current density effect still exists. The bottom-up momentum continues after reaching the feature opening and forms a mushroom shaped top (fig. 1, bottom panel). The current density effect causes more hydrogen production, thus more suppressor deactivation at locations with higher current density. More suppressor deactivation, in return, accelerates higher current density. As a result the deposition rate at fast growing locations increases and the deposition rate at slow growing locations decreases further. This enhancement remains even after the features are fully filled. This uneven plating at different location causes a uniformity issue across the wafer. Several options can be used to solve this uniformity issue without compromising the bottom-up filling. One is to change the plating conditions, such as current density and rotation rate during different stages of the plating. Another is to add a secondary additive to level the surface. Atomplate Co Accelerator XF was tested as a secondary additive for this purpose and it has shown to significantly improve the uniformity. Fig. 1 Cyclic voltammagram (CV) of the Co plating bath in the presence and absence of Atomplate Co Suppressor XF (top). Co bottom up filling of damascene features with pre-plated opening of 4nm (bottom). Figure 1 |
