Specification Driven Design of Phase Locked Loops
| Autor: | Prasenjit Bhowmik, Rupak Ghayal, Prakash Easwaran |
|---|---|
| Rok vydání: | 2009 |
| Předmět: |
Engineering
business.industry Transmitter Topology (electrical circuits) Hardware_PERFORMANCEANDRELIABILITY Power (physics) Phase-locked loop PLL multibit Phase noise Hardware_INTEGRATEDCIRCUITS Electronic engineering business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Frequency modulation Jitter |
| Zdroj: | VLSI Design |
| DOI: | 10.1109/vlsi.design.2009.97 |
| Popis: | The factors that impact the topology and the performance specifications for a Phase locked loop (PLL) is presented. Correct specification of the PLL is critical for optimizing the performance and power of the system. PLL specifications for different systems have been derived and the architectural tradeoffs have been discussed. Three PLL design examples have been presented for WLAN base-bandPLL application, DVB-H receiver base-band PLL application and a high speed (MIPI) transmitter application. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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