Low‐power consumption ternary full adder based on CNTFET
| Autor: | Peiman Keshavarzian, Fereshteh Jafarzadehpour |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Adder
Engineering business.industry 020208 electrical & electronic engineering Transistor 02 engineering and technology 021001 nanoscience & nanotechnology law.invention Carbon nanotube field-effect transistor Control and Systems Engineering law Logic gate Low-power electronics Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Circuit complexity 0210 nano-technology business Ternary operation Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | IET Circuits, Devices & Systems. 10:365-374 |
| ISSN: | 1751-8598 1751-858X |
| Popis: | This paper presents low-power circuits to implement ternary full adder (TFA) using carbon nanotube field-effect transistors (CNTFETs). Besides the unique characteristics of the CNTs, the threshold voltage simple control is the best property to implement ternary logic circuits. Low-complexity, low-power consumption and low-power delay product (PDP) are the benefits of the proposed circuits in comparison with all previous presented designs of TFA. The final proposed TFA is robust and has proper noise margins. The structure of the final proposed TFA is more appropriate to use in ripple adders, since the first ternary half sum generators (THSGs) in all cells produce their outputs in parallel (in the final proposed TFA, the output of the first THSG of the sum-generation unit is also used in the carry-generation unit). The proposed circuits are simulated using HSPICE with 32 nm-CNTFET technology. According to simulation results, the final proposed TFA has reduced the power consumption significantly and results in 86.92 and 97% reductions in terms of the PDP in comparison with two recent proposed designs. |
| Databáze: | OpenAIRE |
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