ASIC synthesis using Architecture Description Language
| Autor: | Zheng Wang, Zoltan E. Rakosi, Xiao Wang, Anupam Chattopadhyay |
|---|---|
| Rok vydání: | 2012 |
| Předmět: |
Architecture description language
business.industry Computer science Hardware description language Application-specific integrated circuit Computer architecture Embedded system High-level synthesis Algorithm design System on a chip business computer Software architecture description computer.programming_language Register-transfer level |
| Zdroj: | VLSI-DAT |
| DOI: | 10.1109/vlsi-dat.2012.6212614 |
| Popis: | Increasing complexity of cutting-edge System-on-Chips (SoCs) is forcing designers to adopt high-level language-based specifications compared to traditional Register Transfer Level (RTL). A range of high-level synthesis tool flows are currently available in commercial and academic realm for modeling the complete SoC or its constituents. The synthesis flows offer automatic generation of optimized RTL based on input specification and several user-directed constraints. Different language specifications are offered for modeling different kind of computing architectures such as processors, Coarse-Grained Reconfigurable Architectures (CGRAs) and Application-Specific Integrated Circuits (ASICs). While the various specification models provide increasing design productivity for the target computing domains, it increases the difficulty to explore the intermediate design points efficiently. In this paper, we propose an approach for high-level synthesis of ASICs based on Architecture Description Languages (ADLs), which are predominantly used for modeling application-specific processors. This helps the designers to explore a wide range of intermediate design points between an ASIC and a weakly programmable processor. We provide several efficient algorithms for automating the high-level synthesis. The ADL-based ASIC synthesis flow is tested with 2 case studies from modern embedded applications. |
| Databáze: | OpenAIRE |
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