A 0.5-V 25-MHz 1-mW 256-Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment—Sure Write Operation by Using Step-Down Negatively Overdriven Bitline Scheme
| Autor: | H. Kiya, S. Kurita, H. Okamoto, Nobutaro Shibata, M. Tan'no, T. Douseki |
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| Rok vydání: | 2006 |
| Předmět: |
Engineering
Hardware_MEMORYSTRUCTURES business.industry 8-bit Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention CMOS Hardware_GENERAL law Logic gate Low-power electronics MOSFET Hardware_INTEGRATEDCIRCUITS Electronic engineering Static random-access memory Electrical and Electronic Engineering Charge-transfer amplifier business Hardware_LOGICDESIGN |
| Zdroj: | IEEE Journal of Solid-State Circuits. 41:728-742 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/jssc.2005.864124 |
| Popis: | Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers. |
| Databáze: | OpenAIRE |
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